CAOTIC: Collaborative Action on Timing Interference

1. Presentation

Project CAOTIC is an ambitious initiative aimed at pooling and coordinating the efforts of major French research teams working on the timing analysis of multicore real-time systems, with a focus on interference due to shared resources. The objective is to enable the efficient use of multicore in critical systems. Based on a better understanding of timing anomalies and interference, taking into account the specificities of applications (structural properties and execution model), and revisiting the links between timing analysis and synthesis processes (code generation, mapping, scheduling), significant progress is targeted in timing analysis models and techniques for critical systems, as well as in methodologies for their application in industry.

In this context, the originality and strength of the CAOTIC project resides in the complementarity of the approaches proposed by the project members to address the same set of scientific challenges: (i) build a consistent and comprehensive set of methods to quantify and control the timing interferences and their impact on the execution time of programs; (ii) define interference-aware timing analysis and real-time scheduling techniques suitable for modern multi-core real-time systems; (iii) consolidate these methods and techniques in order to facilitate their transfer to industry.

Coordinators: Claire Maiza, Lionel Rieg


2. Partners

  • CEA List: M. ASAVOAE (coord.), M. JAN. Timing anomalies, formal hardware/software models, compilation and/or specialised hardware designs.
  • Inria: D. POTOP (coord.). Parallelization of high-performance real-time critical applications onto multicores (Lopht tool), fast and efficient interference analysis.
  • IRISA : I. PUAUT (coord.). WCET analysis (Heptane tool), mapping/scheduling with reduced interference, hardware modeling.
  • IRIT: H. CASSÉ (coord.), T. CARLE, C. ROCHANGE, P. SOTIN. WCET analysis (Otawa tool), scheduling on multicore, timing analysis for GPU accelerators.
  • IRT: E. JENN (coord.). Implementation of industrial applications on multicores, global synthesis and timing analysis workflow, certification.
  • LS2N: J.-L. BÉCHENNEC (coord.), S. FAUCOU, P.-E. HLADIK, L. JEZEQUEL, H.-E. ZAHAF. Hardware/software models, formal methods, GPU interference.
  • LTCI: F. BRANDNER (coord.), D. BLOUIN. Hardware/software models, code generation, hardware timing analysis, timing anomalies.
  • Verimag (Project Coordinator): L. RIEG (coord.), C. MAIZA, E. JAHIER, P. RAYMOND, C. VIGOUROUX, B.FERRES. Implementation of critical dataflow applications on multicores, interference analysis (MIA tool), semantic analysis, timing compositionality.


Univ Grenoble Alpes


Université de Rennes 1


Université de Toulouse 3


Télécom Paris




CEA List

IRT Saint-Exupéry

2.1. Short bibliography pre-CAOTIC

  1. C. Maiza, H. Rihani, J. M. Rivas, J. Goossens, S.Altmeyer, R. I. Davis: A Survey of Timing Verification Techniques for Multi-Core Real-Time Systems. ACM Comput. Surv. 52(3): 56:1-56:38, 2019.
  2. M. Schuh, C. Maiza, J. Goossens, P. Raymond, B. Dinechin: A study of predictable execution models implementation for industrial data-flow applications on a multi-core platform with shared banked memory, RTSS 2020.
  3. P. Raymond, C. Maiza, C. Parent-Vigouroux, F. Carrier, M. Asavoae: Timing analysis enhancement for synchronous program. Real-Time Systems (2015) 1–29.
  4. B. Rouxel, S. Derrien, I. Puaut: Tightening Contention Delays While Scheduling Parallel Applications on Multi-core Architectures. ACM Trans. Embed. Comput. Syst. 16(5): 164:1-164:20, 2017.
  5. B. Rouxel, S. Skalistis, S. Derrien, I. Puaut: Hiding Communication Delays in Contention-Free Execution for SPM-Based Multi-Core Architectures. ECRTS 2019: 25:1-25:24.
  6. K. Didier, D. Potop-Butucaru, G. Iooss, A. Cohen, J. Souyris, P. Baufreton, A. Graillat: Correct-by-Construction Parallelization of Hard Real-Time Avionics Applications on Off-the-Shelf Predictable Hardware. ACM TACO ,16(3): 24:1-24:27, 2019.
  7. T. Carle and H. Cassé: Reducing Timing Interferences in Real-Time Applications Running on Multicore Architectures. In F. Brandner, editor, 18th International Workshop on Worst-Case Execution Time Analysis (WCET), 2018.
  8. T. Degioanni, I. Puaut: StAMP: Static Analysis of Memory Access Profiles for Real-Time Tasks. WCET 2022: 1:1-1:13.
  9. B. Binder, M. Asavoae, F. Brandner, B. Ben Hedia, and M, Jan: The Role of Causality in a Formal Definition of Timing Anomalies. RTCSA 2022.
  10. B. Binder, M. Asavoae, B. Ben Hedia, F. Brandner, and M. Jan: Is This Still Normal? Putting Definitions of Timing Anomalies to the Test. RTCSA 2021.
  11. B. Binder, M. Asavoae, F. Brandner, B. Ben Hedia and M. Jan: Formal modeling and verification for amplification timing anomalies in the superscalar TriCore architecture. Int. J. STTT 2022.
  12. W.-T. Sun, E. Jenn, H. Cassé: Validating Static WCET Analysis: A Method and Its Application. WCET 2019: 6:1-6:10.
  13. V. A. Nguyen, E. Jenn, W. Serwe, F. Lang, R. Mateescu: Using Model Checking to Identify Timing Interferences on Multicore Processors. ERTS 2020.
  14. W.-T. Sun, E. Jenn, H. Cassé: Build Your Own Static WCET analyser: the Case of the Automotive Processor AURIX TC275. ERTS 2020.
  15. Z. Bai, H. Cassé, M. de Michiel, C. Rochange, T. Carle: A Framework for Calculating WCET Based on Execution Decision Diagrams. ACM Transactions on Embedded Computing Systems (TECS).
  16. R. Meunier, T. Carle, T. Monteil: Correctness and Efficiency Criteria for the Multi-Phase Task Model. ECRTS 2022.
  17. M. Adalbert, T. Carle, C. Rochange: PasTiS: building an NVIDIA Pascal GPU simulator for embedded AI applications. ERTS 2022.

3. Results/Publications

To appear

4. Positions/Job offers

4.1. Post-Doc

4.2. Doctorats/Phd thesis